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EM78156E
8-Bit Microcontroller with MASK ROM
Product Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
July 2004
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 4 GENERAL DESCRIPTION ......................................................................................... 1 FEATURES ................................................................................................................. 1 PIN ASSIGNMENT ..................................................................................................... 2 FUNCTION DESCRIPTION ........................................................................................ 4 4.1 Operational Registers......................................................................................... 4
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 R0 (Indirect Addressing Register) .......................................................................4 R1 (Time Clock /Counter)....................................................................................4 R2 (Program Counter) & Stack ...........................................................................5 R3 (Status Register) ............................................................................................6 R4 (RAM Select Register)...................................................................................7 R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................7 RF (Interrupt Status Register) .............................................................................7 R10 ~ R3F ...........................................................................................................7 A (Accumulator)...................................................................................................8 CONT (Control Register).....................................................................................8 IOC5 ~ IOC6 (I/O Port Control Register) ............................................................8 IOCA (Prescaler Counter Register).....................................................................9 IOCB (Pull-down Control Register) .....................................................................9 IOCC (Open-drain Control Register)...................................................................9 IOCD (Pull-high Control Register).....................................................................10 IOCE (WDT Control Register) ...........................................................................10 IOCF (Interrupt Mask Register).........................................................................11
4.2
Special Purpose Registers ................................................................................. 8
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9
4.3 4.4 4.5
TCC/WDT & Prescaler ..................................................................................... 11 I/O Ports ........................................................................................................... 12 RESET and Wake-up ....................................................................................... 15
4.5.1 4.5.2 RESET ..............................................................................................................15 The Status of RST, T, and P of STATUS Register .............................................19
4.6 4.7
Interrupt ............................................................................................................ 20 Oscillator .......................................................................................................... 22
4.7.1 4.7.2 4.7.3 Oscillator Modes................................................................................................22 .Crystal Oscillator/Ceramic Resonators(XTAL) .................................................22 External RC Oscillator Mode.............................................................................23
4.8 4.9
CODE Option Register ..................................................................................... 25 Power On Considerations ................................................................................ 25
4.10 External Power On Reset Circuit...................................................................... 26 4.11 Residue-Voltage Protection.............................................................................. 26 4.12 Instruction Set .................................................................................................. 27 4.13 Timing Diagrams .............................................................................................. 30
Product Specification (V1.3) 07.29.2004 * iii
Contents
5 6
ABSOLUTE MAXIMUNM RATINGS ........................................................................ 31 ELECTRICAL CHARACTERISTICS ........................................................................ 31 6.1 6.2 6.3 DC Electrical Characteristic.............................................................................. 31 AC Electrical Characteristic.............................................................................. 32 Device Characteristic ....................................................................................... 33
APPENDIX
A B Package Types......................................................................................................... 43 Package Information............................................................................................... 43
Specification Revision History
Doc. Version 1.0 1.1 1.2 1.3 Initial version Change set up time period Change Power on reset content Change from EM78P156E to EM78156E Add the Device Characteristic at section 6.3 04/19/2002 07/01/2003 07/29/2004 Revision Description Date
iv *
Product Specification (V1.3) 07.29.2004
EM78156E
8-Bit Microcontroller with MASK ROM
1
GENERAL DESCRIPTION
EM78156E is an 8-bit microprocessor with low-power and high-speed CMOS technology. Integrated into a single chip are on-chip watchdog timer (WDT), RAM, ROM, real time clock/counter, external and interrupt, power down mode, and tri-state I/O.
2
FEATURES
Operating voltage range : 2.3V~5.5V Operating temperature range: 0C~70C Operating frequency rang (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
Low power consumption:
* Less then 2.0 mA at 5V/4MHz * Typically 15 A at 3V/32KHz * Typically 1 A during sleep mode
1K x 13 bits on chip ROM One configuration register to accommodate user's requirements 48x 8 bits on chip registers (SRAM, general purpose register) 2 bi-directional I/O ports 5 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Two clocks per instruction cycle Power down (SLEEP) mode Three available interruptions
* TCC overflow interrupt * Input-port status changed interrupt (wake up from sleep mode) * External interrupt
Programmable free running watchdog timer 8 programmable pull-high pins 7 programmable pull-down pins 8 programmable open-drain pins
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
*1
EM78156E
8-Bit Microcontroller with MASK ROM 2 programmable R-option pins Package types:
* * * *
18 pin DIP 300mil : EM78156EP 18 pin SOP(SOIC) 300mil : EM78156EM 20 pin SSOP 209mil : EM78156EAS 20 pin SSOP 209mil : EM78156EKM
99.9% single instruction cycle commands The transient point of system frequency between HXT and LXT is around 400KHz
3
PIN ASSIGNMENT
NC 1 2 3 EM78156EAS 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC P51 P50 OSCI OSCO VDD P67 P66 P65 P64
P52 P53 TCC /RESET Vss Vss P60/INT P61 P62 P63 1 2 3 EM78156EKM 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P51 P50 OSCI OSCO VDD VDD P67 P66 P65 P64
P52 P53 TCC /RESET Vss P60/INT P61 P62 P63
1 2 3 EM78156EP EM78156EM 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
P51 P50 OSCI OSCO VDD P67 P66 P65 P64
P52 P53 TCC /RESET Vss P60/INT P61 P62 P63
Fig. 1 Pin Assignment Table 1 EM78156EP and EM78156EM Pin Description
Symbol VDD OSCI OSCO TCC /RESET P50~P53 P60~P67 /INT VSS Pin No. 14 16 15 3 4 17, 18, 1, 2 6~13 6 5 Type I I/O I I I/O I/O I Function Power supply. XTAL type: Crystal input terminal or external clock input pin. ERC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50~P52 can be pulled-down by software. P60~P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming. P60~P63 can also be pulled-down by software. External interrupt pin triggered by falling edge. Ground.
2*
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Table 2 EM78156EAS Pin Description
Symbol VDD OSCI OSCO TCC /RESET P50~P53 P60~P67 /INT VSS Pin No. 15 17 16 4 5 18, 19, 2, 3 7~14 7 6 Type I I/O I I I/O I/O I Power supply. XTAL type: Crystal input terminal or external clock input pin. ERC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain keep in reset condition. P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50~P52 can also be pulled-down by software. P60~P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming. P60~P63 can be pulled-down also by software. Function
External interrupt pin triggered by falling edge. Ground.
Table 3 EM78156EKM Pin Description
Symbol VDD OSCI OSCO TCC /RESET P50~P53 P60~P67 /INT VSS Pin No. 15,16 18 17 3 4 19, 20, 1, 2 7~14 7 5, 6 Type I I/O I I I/O I/O I Power supply. XTAL type: Crystal input terminal or external clock input pin. ERC type: RC oscillator input pin. XTAL type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50~P52 can be pulled-down by software. P60~P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming. P60~P63 can also be pulled-down by software. Function
External interrupt pin triggered by falling edge. Ground.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
*3
EM78156E
8-Bit Microcontroller with MASK ROM
4
FUNCTION DESCRIPTION
OSCO /RESET OSCI
WDT timer
TCC
/INT
Oscillator/Timing
Control
Prescaler IOCA
ROM
R2
Stack
RAM
Interrupt Controller
Instruction Register
R3
ALU
R4
R1(TCC)
Instruction Decoder
ACC
DATA & CONTROL BUS
P60//INT P61 P62 P63 P64 P65 P66 P67
IOC6 R6
I/O PORT 6
IOC5 R5
I/O PORT 5
P50 P51 P52 P53
Fig. 2 Function Block Diagram
4.1 Operational Registers
4.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
4.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers. Defined by resetting PAB(CONT-3). The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset. The contents of the prescaler counter will be cleared only when TCC register is written with a value.
4*
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
4.1.3 R2 (Program Counter) & Stack
Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3. Generating 1024x13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all "0"s when under RESET condition. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2,A" allows the contents of `A' to be added to the current PC, and the ninth and tenth bits of the PC are cleared. "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.
PC (A9 ~ A0)
Reset Vector Interrupt Vector
User Memory Space
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5
On-chip Program Memory
Fig. 3 Program Counter Organization
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
*5
EM78156E
8-Bit Microcontroller with MASK ROM
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 RF R0 R1 R2 R3 R4 R5 R6
R PAGE registers (IAR) (TCC) (PC) (Status) (RSR) (Port5) (Port6) Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve (Interrupt Status) IOCA IOCB IOCC IOCD IOCE IOCF IOC5 IOC6 CONT
IOC PAGE registers Reserve (Control Register) Reserve Reserve Reserve (I/O Port Control Register) (I/O Port Control Register) Reserve Reserve Reserve (Prescaler Control Register) (Pull-down Register) (Open-drain Control) (Pull-high Control Register) (WDT Control Register) (Interrupt Mask Register)
General Registers 3F
Fig. 4 Data Memory Configuration
4.1.4 R3 (Status Register)
7 GP2 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C
Bit 0 (C)
Carry flag
Bit 1 (DC) Auxiliary carry flag Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
6*
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT time-out. Bit5 ~7 (GP0 ~ 2) General purpose read/write bits.
4.1.5 R4 (RAM Select Register)
Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode. Bits 6~7 are not used.(read only). The Bits 6~7 set to "1" at all time. Z flag of R3 will set to "1", when R4 content is equal to "3F" When R4=R4+1, R4 content will select as R0. See the configuration of the data memory in Fig. 4.
4.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers. Only the lower 4 bits of R5 are available.
4.1.7 RF (Interrupt Status Register)
7 6 5 4 3 2 EXIF 1 ICIF 0 TCIF
"1" means interrupt request, and "0" means no interrupt occur. Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software. Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by software. Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. Bits 3 ~ 7 Not used. RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. Note that the result of reading RF is the "logic AND" of RF and IOCF.
4.1.8 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
*7
EM78156E
8-Bit Microcontroller with MASK ROM
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding It cannot be addressed.
4.2.2 CONT (Control Register)
7 6 /INT 5 TS 4 TE 3 PAB 2 PSR2 1 PSR1 0 PSR0
Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: transition on TCC pin Bit 6 (/INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instructions Bit 7 Not used.
CONT register is both readable and writable.
4.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
8* Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Only the lower 4 bits of IOC5 can be defined. IOC5 and IOC6 registers are both readable and writable.
4.2.4 IOCA (Prescaler Counter Register)
IOCA register is readable. The value of IOCA is equal to the contents of Prescaler counter. Down counter.
4.2.5 IOCB (Pull-down Control Register)
7 /PD7 6 /PD6 5 /PD5 4 /PD4 3 2 /PD2 1 /PD1 0 /PD0
Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin. 0: Enable internal pull-down 1: Disable internal pull-down Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin. Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin. Bit 3 Not used.
Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin. Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin. Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin. Bit 7 (/PD7) Control bit is used to enable the pull-down of P63 pin. IOCB Register is both readable and writable.
4.2.6 IOCC (Open-drain Control Register)
7 OD7 6 OD6 5 OD5 4 OD4 3 OD3 2 OD2 1 OD1 0 OD0
Bit 0 (OD0) Control bit used to enable the open-drain of P60 pin. 0: Disable open-drain output 1: Enable open-drain output Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin. Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin. Bit 3 (OD3) Control bit is used to enable the open-drain of P63 pin. Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin. Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
*9
EM78156E
8-Bit Microcontroller with MASK ROM Bit 6 (OD6) Bit 7 (OD7) Control bit is used to enable the open-drain of P66 pin. Control bit is used to enable the open-drain of P67 pin.
IOCC Register is both readable and writable.
4.2.7 IOCD (Pull-high Control Register)
7 /PH7 6 /PH6 5 /PH5 4 /PH4 3 /PH3 2 /PH2 1 /PH1 0 /PH0
Bit 0 (/PH0)
Control bit is used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable internal pull-high
Bit 1 (/PH1) Bit 2 (/PH2) Bit 3 (/PH3) Bit 4 (/PH4) Bit 5 (/PH5) Bit 6 (/PH6) Bit 7 (/PH7)
Control bit is used to enable the pull-high of P61 pin. Control bit is used to enable the pull-high of P62 pin. Control bit is used to enable the pull-high of P63 pin. Control bit is used to enable the pull-high of P64 pin. Control bit is used to enable the pull-high of P65 pin. Control bit is used to enable the pull-high of P66 pin. Control bit is used to enable the pull-high of P67 pin.
IOCD Register is both readable and writable.
4.2.8 IOCE (WDT Control Register)
7 WDTE 6 EIS 5 4 ROC 3 2 1 0 -
Bit 7 (WDTE) Control bit used to enable Watchdog timer. 0: Disable WDT. 1: Enable WDT. WDTE is both readable and writable. Bit 6 (EIS) Control bit is used to define the function of P60(/INT) pin. 0: P60, bi-directional I/O pin. 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 7(a). EIS is both readable and writable.
10 * Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Bit 4 (ROC) ROC is used for the R-option. Setting the ROC to "1" will enable the status of R-option pins (P50P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, user must connect the P51 pin or/and P50 pin to VSS with a 430K external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8. Bits 0~3,5 Not used.
4.2.9 IOCF (Interrupt Mask Register)
7 6 5 4 3 2 EXIE 1 ICIE 0 TCIE
Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bits 3~7 Not used. Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 10. IOCF register is both readable and writable.
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the "WDTC" or "SLEP" instructions. Fig. 5 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal source is from
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 11
EM78156E
8-Bit Microcontroller with MASK ROM internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4 application is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms1 (default).
CLK(=Fosc/2 or Fosc/4)
0 1
Data Bus M U X TS M U X PAB 8-bit Counter SYNC 2 cycles
TCC Pin
1
TCC (R1)
0
TE
0
TCC overflow interrupt
WDT
1
M U X PAB
M U X PAB PSR0~PSR2
IOCA
WTE (in IOCE)
8-to-1 MUX
Initial value
0
1
MUX WDT time-out
PAB
Fig. 5 Block Diagram of TCC and WDT
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also have open-drain output by software. Input status change interrupt (or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. When the R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in enable state, P50~P51 must be programmed as input pins. Under
1
: Vdd = 5V, set up time period = 16.8ms 30% Vdd = 3V, set up time period = 18ms 30%
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
12 *
EM78156E
8-Bit Microcontroller with MASK ROM R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b), 7(C)and Figure 8.
PCRD
Q _ Q
P R C L
D CLK PC W R
PORT
Q _ Q
P R C L
D CLK PD W R
IO D
PDRD 0 1 M U X
NOTE: Pull-down is not shown in the figure. Fig. 6 The Circuit of I/O Port and I/O Control Register for Port 5
PCRD
Q _ Q
P RD CLK C L
PCW R
P 6 0 /I N T PORT B it 6 o f I O C E D P R CLK C L Q _ Q 0 1 M U X PDRD Q _ Q P RD CLK C L PDW R
IO D
T 10
D
P R CLK C L
Q _ Q
IN T
NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60(/INT)
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 13
EM78156E
8-Bit Microcontroller with MASK ROM
PCRD
Q _ Q
P RD CLK C L
PCWR
P61~P67 PORT
Q _ Q 0 1
P RD CLK C L
IOD PDWR
M U X TIN PDRD
D
P R CLK C L
Q _ Q
NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67
IOCE.1
D
P R
Q Interrupt RE.1 ENI Instruction
CLK
_ CQ L
T10 T11
P DRQ
CLK
_ C LQ
P QRD
CLK
_ QC L
T17
DISI Instruction Interrupt (Wake-up from SLEEP)
/SLEP
Next Instruction (Wake-up from SLEEP)
Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
14 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 input status changed Wake-up/Interrupt (I) Wake-up from Port 6 Input Status change (a) Before SLEEP 1. Disable WDT2 (using very carefully) 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 4. Enable interrupt (Set IOCF.1) 5. Execute "SLEP" instruction (b) After Wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction (II) Port 6 Input Status Change Interrupt 1. Read I/O Port 6 (MOV R6,R6) 2. Execute "ENI" 3. Enable interrupt (Set IOCF.1) 4. IF Port 6 change (interrupt) Interrupt vector (008H)
PCRD
VCC
ROC
Q Weakly Pull-up Q
P R C L
D CLK PCWR
PORT
Q
P R C L
D PDWR
IOD
Q
PDRD 0
Rex*
1
M U X
*The Rex is 430K ohm external resistor
Fig. 8 The Circuit of I/O Port with R-option(P50,P51)
4.5 RESET and Wake-up
4.5.1 RESET
A RESET is initiated by one of the following events(1) Power on reset.
2
NOTE: Software disables WDT (watchdog timer) but hardware must be enabled before applying Port 6 Changed Wake-up function. (CODE Option Register and Bit 11 (ENWDT) are set to "1").
* 15
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM (2) /RESET pin input "low",or (3) WDT time-out (if enabled). The device is kept in a RESET condition for a period of approx. 183ms (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig.9. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. When power is switched on, the upper 3 bits of R3 are cleared. The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag). The bits of the IOCA register are set to all "1". The bits of the IOCB register are set to all "1". The IOCC register is cleared. The bits of the IOCD register are set to all "1". Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared. Bits 0~2 of RF and bits 0~2 of IOCF register are cleared. The sleep (power down) mode is asserted by executing the "SLEP" instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by(1) External reset input on /RESET pin, (2) WDT time-out (if enabled), or (3) Port 6 input status changes (if enabled). The first two cases will cause the EM78156E to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up. Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is, [a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be disabled. by software. However, the WDT bit in the option register remains enabled. Hence, the EM78156E can be awakened only by Case 1 or 3.
3
NOTE: Vdd = 5V, set up time period = 16.8ms 30% Vdd = 3V, set up time period = 18ms 30%
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
16 *
EM78156E
8-Bit Microcontroller with MASK ROM [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the EM78156E can be awakened only by Case 1 or 2. Refer to the section on Interrupt. If Port 6 Input Status Change Interrupt is used to wake-up the EM78156E (Case [a] above), the following instructions must be executed before SLEP: MOV A, @xx000110b CONTW CLR R1 MOV A, @xxxx1110b CONTW WDTC MOV A, @0xxxxxxxb IOW RE MOV R6, R6 MOV A, @00000x1xb IOW RF ENI (or DISI) SLEP NOP One problem user should be aware of, is that after waking up from the sleep mode, WDT would enable automatically. The WDT operation (being enabled or disabled) should be handled appropriately by software after waking up from the sleep mode. Table 5 The Summary of the Initialized Values for Registers
Address Name Reset Type Bit Name Power-On N/A IOC5 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC6 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
; Select internal TCC clock
; Clear TCC and prescaler ; Select WDT prescaler
; Clear WDT and prescaler ; Disable WDT
; Read Port 6 ; Enable Port 6 input change interrupt
; Enable (or disable) global interrupt ; Sleep
Bit 7 X U U U C67 1 1 P X 1 1
Bit 6 X U U U C66 1 1 P /INT 0 0
Bit 5 X U U U C65 1 1 P TS 1 1
Bit 4 X U U U C64 1 1 P TE 1 1
Bit 3 C53 1 1 P C63 1 1 P PAB 1 1
Bit 2 C52 1 1 P C62 1 1 P
Bit 1 C51 1 1 P C61 1 1 P
Bit 0 C50 1 1 P C60 1 1 P
N/A
CONT
PSR2 PSR1 PSR0 1 1 1 1 1 1 * 17
EM78156E
8-Bit Microcontroller with MASK ROM
Address
Name
Reset Type Wake-Up from Pin Change Bit Name Power-On
Bit 7 P U P P 0 0 P 0 0
Bit 6 P U P P 0 0 P 0 0
Bit 5 P U P P 0 0 P 0 0
Bit 4 P U P P 0 0 P 0 0
Bit 3 P U P P 0 0 P 0 0
Bit 2 P U P P 0 0 P 0 0
Bit 1 P U P P 0 0 P 0 0
Bit 0 P U P P 0 0 P 0 0
0x00
R0(IAR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x01
R1(TCC)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x02
R2(PC)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
**0/P **0/P **0/P **0/P **1/P **0/P **0/P **0/P
GP2 0 0 P 1 1 1 X 0 0 0 P67 U P P X U U U 1 1 P GP1 0 0 P 1 1 1 X 0 0 0 P66 U P P X U U U 1 1 P GP0 0 0 P U P P X 0 0 0 P65 U P P X U U U 1 1 P T 1 T T U P P X 0 0 0 P64 U P P X U U U 1 1 P P 1 t t U P P P53 U P P P63 U P P X U U U 1 1 P Z U P P U P P P52 U P P P62 U P P EXIF 0 0 P 1 1 P DC U P P U P P P51 U P P P61 U P P ICIF 0 0 P 1 1 P C U P P U P P P50 U P P P60 U P P TCIF 0 0 P 1 1 P
0x03
R3(SR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x04
R4(RSR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x05
P5
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x06
P6
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x0F
RF(ISR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x0A
IOCA
/RESET and WDT Wake-Up from Pin Change
18 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Address
Name
Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
Bit 7 /PD7 1 1 P OD7 0 0 P /PH7 1 1 P WDTE 1 1 1 X U U U U P P
Bit 6 /PD6 1 1 P OD6 0 0 P /PH6 1 1 P EIS 0 0 P X U U U U P P
Bit 5 /PD5 1 1 P OD5 0 0 P /PH5 1 1 P X U U U X U U U U P P
Bit 4 /PD4 1 1 P OD4 0 0 P /PH4 1 1 P ROC 0 0 P X U U U U P P
Bit 3 X U U U OD3 0 0 P /PH3 1 1 P X U U U X U U U U P P
Bit 2 /PD2 1 1 P OD2 0 0 P /PH2 1 1 P X U U U EXIE 0 0 P U P P
Bit 1 /PD1 1 1 P OD1 0 0 P /PH1 1 1 P X U U U ICIE 0 0 P U P P
Bit 0 /PD0 1 1 P OD0 0 0 P /PH0 1 1 P X U U U TCIE 0 0 P U P P
0x0B
IOCB
0x0C
IOCC
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x0D
IOCD
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x0E
IOCE
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x0F
IOCF
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x10~0x2F
R10~R2F
/RESET and WDT Wake-Up from Pin Change
** To jump address 0x08, or to execute the instruction which is next to the "SLEP"
instruction. X: Not used. U: Unknown or don't care. P: Previous value before reset. t: Check Table 6
4.5.2 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events: 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P, listed in Table 6 are used to check how the processor wakes up. Table 7 shows the events that may affect the status of T and P.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 19
EM78156E
8-Bit Microcontroller with MASK ROM Table 6 The Values of RST, T and P after RESET
Reset Type Power on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-Up on pin change during SLEEP mode T 1 P 1
*P
1 0 0 1
*P
0
*P
0 0
*P: Previous status before reset
Table 7 The Status of T and P Being Affected by Events.
Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode T 1 1 0 1 1 P 1 1
*P
0 0
*P: Previous value before reset
VDD
O scillator
D CLK CLR
Q
CLK
Power-on R eset
V oltage D etector
W DTE
WDT
W D T T im eout
Setup T im e
R E SE T
/R E SE T
Fig. 9 Block Diagram of Controller Reset
4.6 Interrupt
The EM78156E has three falling-edge interrupts listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changed.
20 * Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM Any pin configured as output or P60 pin configured as /INT is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the EM78156E from the sleep mode if Port 6 is enabled prior to going into the sleep mode by executing SLEP. When the chip wakes-up, the controller will continue to execute the succeeding address if the global interrupt is disabled or branch to the interrupt vector 008H if the global interrupt is enabled. RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to Fig. 10). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from address 001H.
VCC
D /IRQn CLK
P R C L
Q _ Q RFRD
IRQn INT IRQm ENI/DISI
RF
Q _ Q
P R C L
D CLK IOCFWR
IOD
IOCF /RESET
IOCFRD
RFWR
Fig. 10 Interrupt Input Circuit
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 21
EM78156E
8-Bit Microcontroller with MASK ROM
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78156E can be operated in three different oscillator modes, such as External RC oscillator mode (ERC), High XTAL oscillator mode(HXT), and Low XTAL oscillator mode(LXT). User can select one of them by programming MS and HLF in the CODE option register. Table 8 depicts how these three modes are defined. The up-most limited operation frequency of crystal/resonator on the different VDDs is listed in Table 9. Table 8 Oscillator Modes Defined by MS and HLP
Mode ERC(External RC oscillator mode) HXT(High XTAL oscillator mode) LXT(Low XTAL oscillator mode) MS 0 1 1 HLF
*X
1 0
NOTE 1. X, Don't care 2. The transient point of system frequency between HXT and LXY is around 400 KHz.
Table 9 The Summary of Maximum Operating Speeds
Conditions Two cycles with two clocks VDD 2.3 3.0 5.0 Fxt max.(MHz) 4.0 8.0 20.0
4.7.2 .Crystal Oscillator/Ceramic Resonators(XTAL)
EM78156E can be driven by an external clock signal through the OSCI pin as shown in Fig. 11 below.
OSCI OSCO EM78156E
Ext. Clock
Fig. 11 Circuit for External Clock Input
22 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM In the most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 12 depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. Table 10 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
C1 OSCI EM78156E OSCO RS C2 XTAL
Fig. 12 Circuit for Crystal/Resonator Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz LXT Crystal Oscillator HXT 100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 15) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 23
EM78156E
8-Bit Microcontroller with MASK ROM The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency.
Vcc Rext
OSCI Cext EM78156E
Fig. 13 Circuit for External RC Oscillator Mode Table 11 RC Oscillator Frequencies
Cext Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k Average Fosc 5V,25C 3.92 MHz 2.67 MHz 1.39 MHz 149 KHz 1.39 MHz 940 KHz 480 KHz 52 KHz 595 KHz 400 KHz 200 KHz 21 KHz Average Fosc 3V,25C 3.65 MHz 2.60 MHz 1.40 MHz 156 KHz 1.33 MHz 920 KHz 475 KHz 50 KHz 560 KHz 390 KHz 200 KHz 20 KHz
20 pF
100 pF
300 pF
NOTE 1. Measured on DIP packages. 2. For design reference only. 3. The frequency drift is about 30%
24 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
4.8 CODE Option Register
The EM78156E has a CODE option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution.
Bit0 LVDD Bit1 CLK Bit2 /ENWDT Bit3 HLF Bit4 MS Bit5 -
Bit 0 (LVDD):
Levels of the Operating Voltage. 0: Operating Voltage 2.3V ~ 5.5V, non-power saving. 1: Operating Voltage 4V ~ 5.5V, power saving.
Bit 1 (CLK):
Instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. Refer to the section on Instruction Set.
Bit 2 (/ENWDT): Watchdog timer enable bit. 0: Enable 1: Disable Bit 3 (HLF): XTAL frequency selection 0: XTAL2 type (low frequency, 32.768KHz) 1: XTAL1 type (high frequency) This bit will affect system oscillation only when Bit4(MS) is "1". When MS is"0", HLF must be "0".
NOTE The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 4 (MS):
Oscillator type selection. 0: RC type 1: XTAL type (XTAL1 and XTAL2)
Bit 5:
Reserved. The bit is set to "1" all the time.
4.9 Power On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its steady state. EM78156E POR voltage range is 1.2V~1.8V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78156E will reset and work normally. The
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 25
EM78156E
8-Bit Microcontroller with MASK ROM extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40 K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET.
Vdd /RESET EM78156E Rin C R D
Fig. 14 External Power-Up Reset Circuit
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power on reset. Fig.17 and Fig.18 show how to build a residue-voltage protection circuit.
Vdd 33K EM78156E /RESET 40K 1N4684 Q1 10K
Vdd
Fig. 15 Circuit 1 for the Residue Voltage Protection
26 * Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Vdd EM78156E Q1 /RESET 40K R2 R1
Vdd
Fig. 16 Circuit 2 for the Residue Voltage Protection
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) Change one instruction cycle to consist of 4 oscillator periods. (B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were tested to be true, are executed within two instruction cycles. The instructions that are written to the program counter also take two instruction cycles. Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high. Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as shown in Fig. 5. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 27
EM78156E
8-Bit Microcontroller with MASK ROM The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "R", and affects operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010
HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr
MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R
OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3)
STATUS AFFECTED None C None T,P T,P None None None None None None None None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None
0 0000 0001 0011 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0001 0100 0001 rrrr 01rr rrrr 1000 0000 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr
0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 28 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
STATUS AFFECTED None None None None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
INSTRUCTION BINARY 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
HEX 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk
MNEMONIC SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k
OPERATION R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 001H PC k+A A
1 00kk kkkk kkkk 1 1 1 1 1 01kk 1000 1001 1010 1011 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk
1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1111 kkkk kkkk
NOTE This instruction is applicable to IOC5~IOC6, IOCB~IOCF only. This instruction is not recommended for RF operation. This instruction cannot operate under RF.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 29
EM78156E
8-Bit Microcontroller with MASK ROM
4.13 Timing Diagrams
AC Test Input/Output Waveform
2.4 2.0 0.8 0.4
TEST POINTS
2.0 0.8
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
30 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
5
ABSOLUTE MAXIMUNM RATINGS
Items Temperature under bias Storage temperature Input voltage Output voltage 0C to 70C -65C to 150C Vss-0.3V to Vdd+0.5V Vss-0.3V to Vdd+0.5V Rating
6
ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
(Ta=25 C, VDD=5V5%, VSS=0V)
Symbol FXT ERC IIL VIH1 VIL1 VIHT1 VILT1 VIHX1 VILX1 VIH2 VIL2 VIHT2 VILT2 VIHX2 VILX2 VOH1 VOH1 VOL1 VOL1 IPH IPD ISB1 ISB2
Parameter XTAL: VDD to 3V XTAL: VDD to 5V ERC: VDD to 5V Input Leakage Current for input pins Input High Voltage (VDD=5V) Input Low Voltage (VDD=5V) Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) Clock Input Low Voltage (VDD=5V) Input High Voltage (VDD=3V) Input Low Voltage (VDD=3V) Input High Threshold Voltage (VDD=3V) Input Low Threshold Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5) Output High Voltage (Ports 6) (Schmitt trigger) Output Low Voltage(Port5) Output Low Voltage (Ports 6) (Schmitt trigger) Pull-high current Pull-down current Power down current Power down current
Condition Two cycle with two clocks Two cycle with two clocks R: 5.1K, C: 100 pF VIN = VDD, VSS Ports 5, 6 Ports 5, 6 /RESET,TCC(Schmitt trigger) /RESET,TCC(Schmitt trigger) OSCI OSCI Ports 5, 6 Ports 5, 6 /RESET,TCC(Schmitt trigger) /RESET,TCC(Schmitt trigger) OSCI OSCI IOH = -12.0 mA IOH = -12.0 mA IOL = 12.0 mA IOL = 12.0 mA Pull-high active, input pin at VSS Pull-down active, input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled
Min DC DC
Typ.
Max 8.0 20.0 F30% 1
Unit MHz MHz KHz A V V V
F30% 940 2.0
0.8 2.0 0.8 3.5 1.5 1.5 0.4 1.5 0.4 2.1 0.9 2.4 2.4 0.4 0.4 -50 25 -70 50 1 -240 120 2 10
V V V V V V V V V V V V V A A A A * 31
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Symbol ICC1 Parameter Operating supply current (VDD=3V) at two cycles/four clocks Operating supply current (VDD=3V) at two cycles/four clocks Operating supply current (VDD=5.0V) at two cycles/two clocks Operating supply current (VDD=5.0V) at two cycles/four clocks Condition /RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT disabled /RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled Min 15 Typ. 15 Max 30 Unit A
ICC2
20
35
A
ICC3
2.0
mA
ICC4
4.0
mA
6.2 AC Electrical Characteristic
(Ta=25 C, VDD=5V5%, VSS=0V)
Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Cload=20pF Ta = 25C Ta = 25C Ta = 25C Crystal type RC type Conditions Min 45 100 500 (Tins+20)/N* 11.8 2000 11.8 16.8 0 20 50 21.8 16.8 21.8 Typ 50 Max 55 DC DC Unit % ns ns ns ms ns ms ns ns ns
* N= selected prescaler ratio.
32 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
6.3 Device Characteristic
The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristic illustrated herein are not guaranteed for it accuracy. In some graphs, the data maybe out of the specified warranted operating range.
Vih max (0 Vih typ 25 Vih min (0
to 70 to 70
) )
Vil max (0 Vil typ 25 Vil min (0
to 70 to 70
) )
Fig. 17 Vih, Vil of Port6 vs. VDD
Typ 25 Max(0 to 70 )
Min(0
to 70
)
Fig. 18 Vth (Threshold voltage) of Port5 vs. VDD
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 33
EM78156E
8-Bit Microcontroller with MASK ROM
Min 70 Min 70 Typ 25 Min 0 Typ 25
Min 0
Fig. 19 Port5 and Port6 Voh vs. Ioh, DD=5V
Fig. 20 Port5 and Port6 Voh vs. Ioh, VDD=3V
34 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Max 0 Typ 25
Max 0 Typ 25
Iol(mA)
Min 70
Min 70
Fig. 22 Port5, Port6 Vol vs. Iol, VDD = 3V
Fig. 21 Port5, Port6 Vol vs. Iol, VDD = 5V
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 35
EM78156E
8-Bit Microcontroller with MASK ROM
Max 70
Typ 25
Min 0
Fig. 23 WDT time out period vs. VDD,perscaler set to 1:1
36 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Cext = 100pF, Typical RC Frequency vs. VDD
R = 3.3K
R = 5.1K
R = 10K
R = 100K
Fig. 24 Typical RC OSC Frequency vs. VDD (Cext= 100pF, Temperature at 25
)
VDD = 5V
VDD = 3V
Fig. 25 Typical RC OSC Frequency vs. VDD (R and C are ideal components)
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 37
EM78156E
8-Bit Microcontroller with MASK ROM Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows: ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enable ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enable ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enable
Typical ICC1 and ICC2 vs. Temperature
Current (uA)
Typ ICC2 Typ ICC1
Temperature ( )
Fig. 26 Typical operating current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
Max ICC2 Max ICC1
Fig. 27 Maximum operating current (ICC1 and ICC2) vs. Temperature
38 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Typical ICC3 and ICC4 vs. Temperature
Typ ICC4
Typ ICC3
Fig. 28 Typical operating current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
Max ICC4
Current (mA)
Max ICC3
Temperature ( )
Fig. 29 Maximum operating current (ICC3 and ICC4) vs. Temperature
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 39
EM78156E
8-Bit Microcontroller with MASK ROM Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as follows: ISB1: VDD=5V, WDT disable ISB2: VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
Current (uA)
Typ ISB2
Typ ISB1
Temperature ( )
Fig. 30 Typical standby current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
Max ISB2
Current (uA)
Max ISB1
Temperature ( )
Fig. 31 Maximum standby current (ISB1 and ISB2) vs. Temperature
40 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Fig. 32 Operating voltage in temperature range from 0
to 70
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 41
EM78156E
8-Bit Microcontroller with MASK ROM
EM78156E-J HXT V-I
Fig. 33 Operating current range (based on high Freq. @ =25
) vs. Voltage
Fig. 34 Operating current range (based on low Freq. @ =25
) vs. Voltage
42 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
APPENDIX A Package Types
MASK MCU EM78156EP EM78156EM EM78156EAS EM78156EKM Package Type DIP SOP SSOP SSOP Pin Count 18 18 20 20 Package Size 300 mil 300 mil 209 mil 209 mil
B Package Information
18-Lead Plastic Dual in line (PDIP) 300 mil
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
* 43
EM78156E
8-Bit Microcontroller with MASK ROM 18-Lead Plastic Small Outline (SOP) 300 mil
20-Lead Plastic Small Outline (SSOP)
209 mil
44 *
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)

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